1. Field of the Invention
The present invention relates to a system controller, a snoop tag modification method and an information processing apparatus for controlling a snoop tag having copy information on a cache tag of each CPU to ensure coherency of a cache memory, in a multiprocessor system.
2. Description of the Related Art
In recent years, information processing apparatuses have been extensively used in various areas. Accordingly, high processing capacity of chipsets in multiprocessor configurations has been required more than ever before.
FIG. 23 illustrates an example of a multiprocessor system. In the multiprocessor system shown in FIG. 23, CPUs 520a and 520b are connected to a system controller 510 via a CPU bus 530a, and CPUs 520c and 520d are connected to the system controller 510 via a CPU bus 530c. The CPUs 520a-520d include cache memories 521a-521d and cache tags 522a-522d respectively. In addition, the system controller 510 includes snoop tags 511a-511d corresponding to the cache tags 522a-522d in the respective CPUs 520a-520d. 
States and addresses of data stored in the cache memory 521 are recorded in the cache tag 522. Copy information on the corresponding cache tag 522 is recorded in the snoop tag 511.
FIG. 24 shows an example of conventional cache tags/snoop tags. FIG. 24 shows a relationship among the CPU 520a and the CPU 520b which are connected to the same CPU bus 530a shown in FIG. 23 and the system controller 510. Entries of one same index are shown in the cache tag 522a in the CPU 520a, the cache tag 522b in the CPU 520b, and the snoop tag 511a and the snoop tag 511b in the system controller 510. It should be noted that the cache memory 521 is assumed be controlled by a 4-Way set associative method.
The snoop tag 511a in the system controller 510 retains the copy information on the corresponding cache tag 522a. Also, the snoop tag 511b in the system controller 510 retains the copy information on the corresponding cache tag 522b. In FIG. 24, an entry registered in the cache tag 522 has a valid entry in the corresponding snoop tag 511.
A state and an address are described for each entry in the cache tag 522 and the snoop tag 511 shown in FIG. 24. Here, MESI protocol is used for cache coherency. The MESI protocol is one type of cache coherency protocols, and divides each line of the cache into M (Modified) denoting a modified state, E (Exclusive) denoting an exclusive state, S (Shared) denoting a shared state and I (Invalid) denoting an invalid state, then controls them.
FIG. 25 illustrates Eviction. Eviction is to instruct to perform a cache ejection process with respect to the CPU 520 from the system controller 510. Hereinafter, Eviction will be described by using an example of FIG. 25.
First, as shown in phase 0, it is assumed that one same index is blank both in the cache tag 522 and the snoop tag 511. At this point, when the CPU 520 reads a block number A, the block number A is registered in the cache tag 522 and the snoop tag 511 respectively as shown in phase 1. Furthermore, when the CPU 520 continuously reads the same index through a block number B, a block number C and a block number D, they become way-full as shown in phase 2.
In such a way-full state, if the CPU 520 hopes to further read a block number E of the same index, the CPU 520 has to delete any data in the cache tag 522 first. Here, the block number A is to be deleted. If the CPU 520 does not support a cache replacement request, and the state of the block number A is not M (Modified), a silent drop occurs at the block number A in the CPU 520. As shown in phase 3, the block number A is deleted in the cache tag 522. It should be noted that the silent drop is to discard data without notifying others of it.
Similarly, when the system controller 510 receives reading of the block number E from the CPU 520, the system controller 510 will also register the block number E and has to delete any one of data in the snoop tag 511. Here, the block number B is to be deleted. At this point, since there is an inclusion rule of “an entry existing in the cache tag 522 has to exist in the snoop tag 511”, the system controller 510 has to cause the CPU 520 to also delete the entry which the system controller 510 has deleted, and thereby needs to issue an ejection request to the CPU 520, as shown in phase 4. This ejection request is referred to as Eviction. Eventually, there will be blank entry in both of the cache tag 522 and the snoop tag 511, and thereby the block number E can be registered in both respectively, as shown in phase 5.
It should be noted that prior art documents describing techniques related to the system controller for ensuring the coherency of the cache memory in the multiprocessor system include, for example, Patent Document 1 (Japanese Patent Laid-Open number 2001-43204). Patent Document 1 describes a technique related to a cache memory control apparatus, which corresponds to the above described system controller 510, for ensuring the coherency of the cache memory by a bus snoop method. However, the technique described in Patent Document 1 cannot solve problems described below.
In the system without the cache replacement request from the CPU 520, the snoop tag 511 in the system controller 510 often has the entry having already been replaced, that is, having been dropped I (Invalid), by the CPU 520 (refer to phase 3 in FIG. 25). Due to this characteristic, even though the CPU 520 is still not way-full, the system controller 510 may misunderstand that the CPU 520 is way-full and issue Eviction (refer to phase 4 in FIG. 25).
Thereby, the system controller 510 happens to issue more data ejection requests than necessary with respect to the CPU 520. Therefore, when the entry subjected to the data ejection request is an entry still being required by the CPU 520, the CPU 520 has to issue a read request to obtain the entry again later at the time when the CPU 520 requires the entry, which has been a major cause of degrading system performance.